In recent years there has been a demand for electronic components used in mobile telephones, wireless LANs and the like, to be made compact and low-profile in order to cope with increasing levels of functionality and reductions in equipment size. In particular with regard to making components low-profile, there is a demand for the material to be used in these components to be a high-strength material capable of being made thin. With regard also to size reductions, high functionality within a confined area has been achieved by mounting ICs and the like directly on a multilayer wiring substrate consisting of glass ceramic or the like. For the mounting of ICs flip-chip-mountings and the like are becoming widely used, from the viewpoint of minimizing the mounting area when ICs are mounted in this way.
In such flip chip mounting, high dimensional accuracy and surface flatness are required more than before for the surface of the multilayer wiring substrate, which is serves as a mounting surface, in order to cope with market trends to reduce the size of the ICs and increase the number of pins.
For multilayer wiring substrates provided with integrated LSIs and various types of electronic components, ceramics or glass ceramics are used as materials in order to meet demands such as those described above and also from the viewpoint of ensuring reliability. Alumina is typically used as the ceramic material. Glass ceramic materials are produced by being by mixing a glass material and a ceramic material known as an aggregate and then by sintering.
Alumina generally has advantages such as high strength and excellent heat resistance, and it thus occupies a large proportion of the ceramics used for the abovementioned multilayer wiring substrates. However, on the other hand, it also has drawbacks in that its dielectric constant is large, and it is therefore likely to cause delays in signal transmission. Moreover, alumina has a high sintering temperature of 1500° C. or more, and thus tungsten (W) or molybdenum (Mo), which have a high melting point and high electrical resistivity, must be used for wiring in the inner layers, and there are thus problems in that the electrical resistance becomes large if the wiring is made extremely fine.
On the other hand, glass ceramic materials have advantages that resolve the problems arising with alumina. Glass ceramic materials are being used more widely in consideration of its advantages of the dielectric constant being low, and further of allowing the use of low-resistance metal materials having a low melting point, such as Cu, Ag or Ag—Pd, as inner layer conductors or surface conductors, or for via conductors to connect the above two conductors.
In general, with glass ceramic multilayer wiring substrates employing glass ceramics it is straightforward to implement inter-layer circuits having a three-dimensional structure, and they thus provide good design flexibility. This is thus becoming a critical technology in the marketplace for high-frequency components, the size of which is reducing while the level of functionality is increasing.
Further, for multilayer wiring substrates having a three-dimensional structure, deformations such as warping and unevenness are likely to occur during the manufacturing process due to the three-dimensional structure. In particular, in areas in the vicinity of connection terminals formed by surface conductors on the surface of a multilayer wiring substrate during flip chip mounting of ICs, a flat surface condition is desirable in order to achieve satisfactory mounting with the IC. If an irregularity is larger than the height of the flip-chip pad on the IC, there is a high probability of mounting failure. Further, it is thought that the cause of such deformation is due to discrepancies between the sintering behaviors of the inner layer conductors or via conductors and the glass ceramic material, and thus matching the sintering behaviors of via conductors and the glass ceramic material is, in particular, a critical technology.
In particular, because via conductors are formed in a direction perpendicular to the substrate surface, the flatness of the substrate surface tends to deteriorate as the ratio between the length of the via conductors, in a direction perpendicular to the surface of the wiring substrate, and the thickness of the substrate increases. Naturally, when via conductors which extend in a direction perpendicular to the surface are connected by direct connection, the flatness of the substrate surface deteriorates more as the total length of the via conductors increases. From the viewpoint of increasing the degree of design freedom, it is desirable for via conductors to be connected together directly, and it is thus critical for the sintering behavior of via conductors to be matched.
Further, in some cases via conductors are used not only for electrical wiring but also as a heat conduction path for dissipating heat from ICs. In such cases it is common for the via conductors to be constructed in such a way that they penetrate through the multilayer wiring substrate, and they thus serve to allow heat generated when the IC is operating to escape to the outside through the via conductors. Forming such penetrating via conductors is likely to make the impact of via conductors be felt more readily, and to make deformation more likely to occur. However, in the current situation in which ICs are required to have good heat dissipation characteristics, there is an increasing demand for such structures, and thus controlling the sintering behavior of via conductors and glass ceramics is becoming critical.
With glass ceramic materials, a synergistic effect typically acts during sintering through the combination of a glass material and a ceramic material, and thus the properties of the resulting ceramic multilayer wiring substrate (dielectric constant, loss characteristics, thermal expansion coefficient, sintering temperature, bending strength and the like) can be controlled. Therefore, it is a technological challenge to find the optimal combination and to achieve a stable composition and a structure such that uniform properties can be exhibited at all times.
Further, multilayer wiring substrates employing glass ceramic materials contain glass as a main component, and they thus have the characteristic that they are sensitive to impacts and a crack is easily caused. To overcome this drawback, attempts have been made to improve the strength by formulating ceramic fillers.
Investigations into improvements of each of the problems discussed hereinabove are being made, but in order to realize a multilayer wiring substrate that is exceptionally useful in practice, a significant point to consider is how to solve all of the problems simultaneously.
For example, from the viewpoint of substrate strength, Japanese Patent Kokai 2007-103836 proposes using a tabular alumina filler in order to improve the strength of a glass ceramic multilayer wiring substrate, but adequate substrate strength is not obtained. Accordingly, Japanese Patent Kokai 2010-100517 (U.S. counterpart is published as US 2010/0080981) proposes providing a high-strength multilayer wiring substrate in which the orientation of a ceramic filler is improved by formulating a ceramic filler having a large aspect ratio.
Further, in general it is difficult to obtain a high degree of dimensional accuracy in multilayer wiring substrates produced by sintering, due to variations in the amount of shrinkage during sintering. As a countermeasure to this, it has been proposed to use a sintering technique known as a non-shrink sintering technique in which sintering shrinkage is suppressed.
Further, with multilayer wiring substrates which are sintered using a typical sintering technique, it is known that undulations are likely to occur on the substrate surface, causing a deterioration in the flatness of the multilayer wiring substrate surface, due to the effects of the sintering behavior of inner layer conductors comprising low-resistance metal materials having a low melting point, such as Cu, Ag or Ag—Pd. It has also been proposed to use a sintering technique known as a non-shrink sintering technique, in which sintering shrinkage is suppressed, as one countermeasure to these problems.
For example, Japanese Patent Kokai 2005-26722 proposes a multilayer glass ceramic substrate having improved flatness and dimensional accuracy, employing non-shrink sintering.
Non-shrink sintering techniques have also been confirmed to be effective in suppressing warping of the substrate during sintering, and they are thus being used as very effective techniques for producing multilayer wiring substrates which are required to be low-profile and increased in size.
More specifically, non-shrink sintering techniques predominantly employ a method in which shrinkage in the x-y directions is suppressed by joining a soluble green sheet (shrinkage-suppressing green sheet) of a sintering-resistant material that does not sinter at the sintering temperature of the glass ceramic substrate wiring material to one surface or both surfaces of an unsintered glass ceramic laminated body.
In a processing method employing such a non-shrink sintering technique, in a glass ceramic multilayer wiring substrate manufactured by laminating a plurality of glass ceramic green sheets, multiple via holes are formed in order to connect the inter-layer circuits electrically and the interior of the via holes is filled with an electrically conductive electrode material.
At this time, the via holes consist of electrically conductive metal powder, organic binder and solvent, and thus the volume thereof shrinks during the course of the sintering. The electrically conductive metal powder is designed such that it shrinks to the same extent as the glass ceramic, but with non-shrink sintering the shrinkage-suppressing effect of the shrinkage-suppressing green sheet with respect to the electrically conductive metal powder is poor, and the sintering behavior is likely to differ from that of the glass ceramic. Various types of electrically conductive metal powder have been investigated to deal with this situation, but this remains one problem of non-shrink sintering technology.
In general, with glass ceramics, although shrinkage in the x-y directions is suppressed by means of the soluble green sheet made of a sintering-resistant material, in contrast, shrinkage in the z direction increases. Therefore, in non-shrink sintering, there is a large difference in shrinkage of the glass ceramic compared with the electrically conductive metal in the via hole portions. As a result, after sintering, the via conductors (the via hole portions filled with the electrically conductive metal) are likely to be higher than the height of the glass ceramic, and are likely to protrude to the outside, and, thus, the substrate is likely to become deformed. The degree of deformation tends to increase as the proportion occupied by via conductors increases. Various types of improvements have been considered to deal with this situation. When non-shrink sintering is employed in this way, it becomes more difficult than with ordinary sintering to match the shrinkage behavior of the via conductors, and thus controlling the shrinkage behavior is critical.
As electronic products become more low-profile in their height, there is a need for the glass ceramic substrates used in multilayer wiring substrates to be made even thinner. Further, as circuits become more complicated and finer, the structure of the electrodes is becoming more complicated, and thus an increasing amount of stress also acts on the glass ceramic substrate. Moreover, as mounted components such as ICs become yet more compact, even greater accuracy in alignment for mounting is required, and as a result there is a need for yet further improvements in the dimensional accuracy of multilayer wiring substrates, which serves as a mounting body. Also, in relation to IC mounting, flip chip mounting is becoming more prevalent, and thus multilayer wiring substrates are facing increasing demands in regard to warping and surface flatness. There is thus a demand for a multilayer wiring substrate which has greater strength than the prior art, while having better dimensional accuracy, no warping, and excellent surface flatness.
However, the inventors have found through investigations that in relation to glass ceramic multilayer wiring substrates such as those proposed in the above mentioned Japanese Patent Kokai 2007-103836 and Japanese Patent Kokai 2010-100517, although strength and dimensional accuracy are adequate, the substrate is not satisfactory in terms of warping and surface flatness.
Further, Japanese Patent Kokai 2005-26722 proposes a multilayer glass ceramic substrate with reduced warping of the substrate and improved dimensional accuracy, but a sufficiently high substrate strength cannot be anticipated. Further, even though warping of the substrate can be improved using Japanese Patent Kokai 2005-26722, it is difficult to improve the flatness of the surface using non-shrink sintering techniques alone. This is because when non-shrink sintering techniques are applied to multilayer wiring substrates having via conductors, it is more difficult to match the shrinkage behavior of the via conductors than when ordinary sintering is employed.